@IEEEtranBSTCTL{bstctl:etal,
  CTLuse_forced_etal = {yes},
  CTLmax_names_forced_etal = {3},
}

@IEEEtranBSTCTL{bstctl:nodash,
  CTLdash_repeated_names = {no},
}

@IEEEtranBSTCTL{bstctl:simpurl,
  CTLname_url_prefix = {Available: },
}

@book{lamport94,
    author    = "Leslie Lamport",
    title     = "{\LaTeX: A Document Preparation System}",
    year      = "1994",
    publisher = "Addison-Wesley",
    edition = "2nd",
    address   = "Reading, Massachusetts",
}

@book{goossens93,
    author    = "Michel Goossens and Frank Mittelbach and Alexander Samarin",
    title     = "The LaTeX Companion",
    year      = "1993",
    publisher = "Addison-Wesley",
    address   = "Reading, Massachusetts",
}

@misc{micro46,
    author = "Matthew Farrens and others",
    title = "{MICRO'46 Conference Site}",
    year = "2013",
    url = "http://www.microarch.org/micro46/",
}

@misc{ARM11-WhitePaper-BigLittle,
    author = "ARM",
    title = "{Big.LITTLE Processing with ARM Cortex-A15 \& Cortex-A7}",
    year = "2011",
    url = "http://www.arm.com/",
}

@misc{coremark,
    author="EEMBC",
    title="Coremark",
    url="http://coremark.org/",
}
@inproceedings{Kumar04-SIHM,
 author = {Rakesh Kumar and Dean M. Tullsen and Parthasarathy Ranganathan and Norman P. Jouppi and Keith I. Farkas},
 title = "{Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance}",
booktitle = "{ISCA}",
 year = {2004},
 pages = {64},
 publisher = {IEEE Computer Society},
 }

@inproceedings{Kumar03-SIHM,
 author = {Rakesh Kumar and Keith I. Farkas and Norman P. Jouppi and Parthasarathy Ranganathan and Dean M. Tullsen},
 title = "{Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction}",
booktitle = "{MICRO}",
 year = {2003},
 pages = {81},
 publisher = {IEEE Computer Society},
 }

@inproceedings{Kumar06-PACT-SIHM,
 author = {Rakesh Kumar and Dean M. Tullsen and Norman P. Jouppi},
 title = {Core architecture optimization for heterogeneous chip multiprocessors},
booktitle = "{PACT}",
 year = {2006},
 isbn = {1-59593-264-X},
 pages = {23--32},
 location = {Seattle, Washington, USA},
 doi = {http://doi.acm.org/10.1145/1152154.1152162},
 publisher = {ACM Press},
 address = {New York, NY, USA},
 }

@inproceedings{Clark08-ISCA-VEAL,
 author = {Clark, Nathan and Hormati, Amir and Mahlke, Scott},
 title = {VEAL: Virtualized Execution Accelerator for Loops},
booktitle = "{ISCA}",
 year = {2008},
 isbn = {978-0-7695-3174-8},
 pages = {389--400},
 doi = {http://dx.doi.org/10.1109/ISCA.2008.33},
 publisher = {IEEE Computer Society},
 address = {Washington, DC, USA},
 }

@inproceedings{Venkatesh10-ASPLOS-CCores,
 author = {Venkatesh, Ganesh and Sampson, Jack and Goulding, Nathan and Garcia, Saturnino and Bryksin, Vladyslav and Lugo-Martinez, Jose and Swanson, Steven and Taylor, Michael Bedford},
 title = {Conservation cores: reducing the energy of mature computations},
 booktitle = "{ASPLOS '10: Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems}",
 year = {2010},
 isbn = {978-1-60558-839-1},
 pages = {205--218},
 location = {Pittsburgh, Pennsylvania, USA},
 doi = {http://doi.acm.org/10.1145/1736020.1736044},
 publisher = {ACM},
 address = {New York, NY, USA},
 }

@ARTICLE{Goulding11-IEEEMICRO-GreenDroid,
author={Goulding-Hotta, N. and Sampson, J. and Venkatesh, G. and Garcia, S. and Auricchio, J. and Huang, P. and Arora, M. and Nath, S. and Bhatt, V. and Babb, J. and Swanson, S. and Taylor, M.},
journal={IEEE Micro},
title={The {G}reen{D}roid Mobile Application Processor: An Architecture for Silicon's Dark Future},
year={2011},
month={Mar./Apr.},
volume={31},
number={2},
pages={86-95},
keywords={GreenDroid mobile application processor;dark silicon;energy efficient design;modern processor design;silicon dark future;smart phone application;elemental semiconductors;mobile computing;mobile handsets;multiprocessing systems;silicon;},
doi={10.1109/MM.2011.18},
ISSN={0272-1732},}

@inproceedings{Dennard74-JSSC-MOSFET_Scaling,
 author = {R.H. Dennard and F. H. Gaensslen and V. L. Rideout and E. Bassous and A. R. LeBlanc},
 title = "{Design of Ion-Implanted MOSFET's with Very Small Physical Dimensions}",
 booktitle = "{IEEE Journal of Solid-State Circuits}",
 year = {1974},
 month={October}
 }

@article{gem5,
 author = {Binkert, Nathan and Beckmann, Bradford and Black, Gabriel and Reinhardt, Steven K. and Saidi, Ali and Basu, Arkaprava and Hestness, Joel and Hower, Derek R. and Krishna, Tushar and Sardashti, Somayeh and Sen, Rathijit and Sewell, Korey and Shoaib, Muhammad and Vaish, Nilay and Hill, Mark D. and Wood, David A.},
 title = {The gem5 simulator},
 journal = {SIGARCH Comput. Archit. News},
 issue_date = {May 2011},
 volume = {39},
 number = {2},
 month = aug,
 year = {2011},
 issn = {0163-5964},
 pages = {1--7},
 numpages = {7},
 url = {http://doi.acm.org/10.1145/2024716.2024718},
 doi = {10.1145/2024716.2024718},
 acmid = {2024718},
 publisher = {ACM},
 address = {New York, NY, USA},
} 


@inproceedings{mcpat,
 author = {Li, Sheng and Ahn, Jung Ho and Strong, Richard D. and Brockman, Jay B. and Tullsen, Dean M. and Jouppi, Norman P.},
 title = {McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures},
 booktitle = {Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture},
 series = {MICRO 42},
 year = {2009},
 isbn = {978-1-60558-798-1},
 location = {New York, New York},
 pages = {469--480},
 numpages = {12},
 url = {http://doi.acm.org/10.1145/1669112.1669172},
 doi = {10.1145/1669112.1669172},
 acmid = {1669172},
 publisher = {ACM},
 address = {New York, NY, USA},
} 

@misc{spec2000,
        author = {{Standard Performance Evaluation Corporation}},
        title = {{SPEC} {CPU} 2000 Benchmark Specifications},
        note = {{SPEC2000 Benchmark Release}},
        year = 2000
}

@misc{spec2006,
        author = {{Standard Performance Evaluation Corporation}},
        title = {{SPEC} {CPU} 2006 Benchmark Specifications},
        note = {{SPEC2006 Benchmark Release}},
        year = 2006
}

@inproceedings{Clark05-ISCA-CustomISA,
 author = {Nathan Clark and Jason Blome and Michael Chu and Scott Mahlke and Stuart Biles and Krisztian Flautner},
 title = {An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors},
booktitle = "{ISCA}",
 year = {2005},
 pages = {272--283},
 publisher = {IEEE Computer Society},
 }



@inproceedings{HOROWITZ10-ISCA-ASICcomparison,
 author = {Hameed, Rehan and Qadeer, Wajahat and Wachs, Megan and Azizi, Omid and Solomatnikov, Alex and Lee, Benjamin C. and Richardson, Stephen and Kozyrakis, Christos and Horowitz, Mark},
 title = {Understanding sources of inefficiency in general-purpose chips},
booktitle = "{ISCA}",
 year = {2010},
 isbn = {978-1-4503-0053-7},
 pages = {37--47},
 location = {Saint-Malo, France},
 doi = {http://doi.acm.org/10.1145/1815961.1815968},
 publisher = {ACM},
 address = {New York, NY, USA},
 }


@article{Dally08-CAL-ELM,
 author = {Balfour, James and Dally, William and Black-Schaffer, David and Parikh, Vishal and Park, JongSoo},
 title = {An Energy-Efficient Processor Architecture for Embedded Systems},
 journal = {IEEE Comput. Archit. Lett.},
 volume = {7},
 number = {1},
 year = {2008},
 issn = {1556-6056},
 pages = {29--32},
 doi = {http://dx.doi.org/10.1109/L-CA.2008.1},
 publisher = {IEEE Computer Society},
 address = {Washington, DC, USA},
 }

@inproceedings{Sherwood01-PACT-Simpoint,
 author = {Sherwood, Timothy and Perelman, Erez and Calder, Brad},
 title = {Basic Block Distribution Analysis to Find Periodic Behavior and Simulation Points in Applications},
booktitle = "{PACT}",
 year = {2001},
 isbn = {0-7695-1363-8},
 pages = {3--14},
 publisher = {IEEE Computer Society},
 address = {Washington, DC, USA},
 }

@phdthesis{Chakraborty08-THESIS-OverprovisionedCores,
author={Koushik Chakraborty},
title="{Over-provisioned Multicore System}",
school={University of Wisconsin-Madison},
year={2008},
}

@inproceedings{Esmaeilzadeh11-ISCA-DarkSilicon,
  title={Dark Silicon and the End of Multicore Scaling},
  author={Esmaeilzadeh, H. and Blem, E. and Amant, R.S. and Sankaralingam, K. and Burger, D.},
booktitle = "{ISCA}",
  year={2011}
}

@inproceedings{pin,
 author = {Luk, Chi-Keung and Cohn, Robert and Muth, Robert and Patil, Harish and Klauser, Artur and Lowney, Geoff and Wallace, Steven and Reddi, Vijay Janapa and Hazelwood, Kim},
 title = {Pin: building customized program analysis tools with dynamic instrumentation},
 booktitle = {Proceedings of the 2005 ACM SIGPLAN conference on Programming language design and implementation},
 series = {PLDI '05},
 year = {2005},
 isbn = {1-59593-056-6},
 location = {Chicago, IL, USA},
 pages = {190--200},
 numpages = {11},
 url = {http://doi.acm.org/10.1145/1065010.1065034},
 doi = {10.1145/1065010.1065034},
 acmid = {1065034},
 publisher = {ACM},
 address = {New York, NY, USA},
 keywords = {dynamic compilation, instrumentation, program analysis tools},
}

@inproceedings{Kim09-MICRO-Qilin,
  title={Qilin: exploiting parallelism on heterogeneous multiprocessors with adaptive mapping},
  author={Luk, C.K. and Hong, S. and Kim, H.},
  booktitle="{Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture}",
  pages={45--55},
  year={2009},
  organization={ACM}
}

@ARTICLE{Hoste07-IEEEMICRO-MICA, 
author={Hoste, K. and Eeckhout, L.}, 
journal={Micro, IEEE}, 
title={Microarchitecture-Independent Workload Characterization}, 
year={2007}, 
volume={27}, 
number={3}, 
pages={63-72}, 
keywords={computer architecture;microprogramming;computer designers;computer systems;microarchitecture-independent workload characterization;microprocessor design;Application software;Biometrics;Computational modeling;Counting circuits;Design optimization;Hardware;Microarchitecture;Microprocessors;Performance analysis;Solids;measurement techniques;modeling techniques;performance attributes;workload characterization}, 
doi={10.1109/MM.2007.56}, 
ISSN={0272-1732},}

@article{Shelepov09-SIGOPS-HeteroScheduling,
 author = {Shelepov, Daniel and Saez Alcaide, Juan Carlos and Jeffery, Stacey and Fedorova, Alexandra and Perez, Nestor and Huang, Zhi Feng and Blagodurov, Sergey and Kumar, Viren},
 title = {HASS: a scheduler for heterogeneous multicore systems},
 journal = {SIGOPS Oper. Syst. Rev.},
 issue_date = {April 2009},
 volume = {43},
 number = {2},
 month = apr,
 year = {2009},
 issn = {0163-5980},
 pages = {66--75},
 numpages = {10},
 url = {http://doi.acm.org/10.1145/1531793.1531804},
 doi = {10.1145/1531793.1531804},
 acmid = {1531804},
 publisher = {ACM},
 address = {New York, NY, USA},
 keywords = {architectural signatures, asymmetric, heterogeneous, multicore, scheduling},
} 

@article{weka,
 author = {Hall, Mark and Frank, Eibe and Holmes, Geoffrey and Pfahringer, Bernhard and Reutemann, Peter and Witten, Ian H.},
 title = {The WEKA data mining software: an update},
 journal = {SIGKDD Explor. Newsl.},
 issue_date = {June 2009},
 volume = {11},
 number = {1},
 month = nov,
 year = {2009},
 issn = {1931-0145},
 pages = {10--18},
 numpages = {9},
 url = {http://doi.acm.org/10.1145/1656274.1656278},
 doi = {10.1145/1656274.1656278},
 acmid = {1656278},
 publisher = {ACM},
 address = {New York, NY, USA},
} 

@inproceedings{Lukefahr12-MICRO-CompositeCores,
 author = {Lukefahr, Andrew and Padmanabha, Shruti and Das, Reetuparna and Sleiman, Faissal M. and Dreslinski, Ronald and Wenisch, Thomas F. and Mahlke, Scott},
 title = {Composite Cores: Pushing Heterogeneity Into a Core},
 booktitle = {Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture},
 series = {MICRO '12},
 year = {2012},
 isbn = {978-0-7695-4924-8},
 pages = {317--328},
 numpages = {12},
 url = {http://dx.doi.org/10.1109/MICRO.2012.37},
 doi = {10.1109/MICRO.2012.37},
 acmid = {2457508},
 publisher = {IEEE Computer Society},
 address = {Washington, DC, USA},
 keywords = {heterogeneous architecture, core microarchitecure, split pipelines, reactive controller},
} 

@inproceedings{horowitz,
 author = {Azizi, Omid and Mahesri, Aqeel and Lee, Benjamin C. and Patel, Sanjay J. and Horowitz, Mark},
 title = {Energy-performance tradeoffs in processor architecture and circuit design: a marginal cost analysis},
 booktitle = {Proceedings of the 37th annual international symposium on Computer architecture},
 series = {ISCA '10},
 year = {2010},
 isbn = {978-1-4503-0053-7},
 location = {Saint-Malo, France},
 pages = {26--36},
 numpages = {11},
 url = {http://doi.acm.org/10.1145/1815961.1815967},
 doi = {10.1145/1815961.1815967},
 acmid = {1815967},
 publisher = {ACM},
 address = {New York, NY, USA},
 keywords = {co-optimization, design space exploration, design trade-offs, energy efficiency, microarchitecture, optimization},
} 

@article{subsettingSPEC,
 author = {Phansalkar, Aashish and Joshi, Ajay and John, Lizy K.},
 title = {Subsetting the SPEC CPU2006 benchmark suite},
 journal = {SIGARCH Comput. Archit. News},
 issue_date = {March 2007},
 volume = {35},
 number = {1},
 month = mar,
 year = {2007},
 issn = {0163-5964},
 pages = {69--76},
 numpages = {8},
 url = {http://doi.acm.org/10.1145/1241601.1241616},
 doi = {10.1145/1241601.1241616},
 acmid = {1241616},
 publisher = {ACM},
 address = {New York, NY, USA},
} 

@phdthesis{ parsec,
  author = {Christian Bienia},
  title = {Benchmarking Modern Multiprocessors},
  school = {Princeton University},
  year      = {2011},
  month     = {January}
}

@inproceedings{mibench,
 author = {Guthaus, M. R. and Ringenberg, J. S. and Ernst, D. and Austin, T. M. and Mudge, T. and Brown, R. B.},
 title = {MiBench: A free, commercially representative embedded benchmark suite},
 booktitle = {Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop},
 series = {WWC '01},
 year = {2001},
 isbn = {0-7803-7315-4},
 pages = {3--14},
 numpages = {12},
 url = {http://dx.doi.org/10.1109/WWC.2001.15},
 doi = {10.1109/WWC.2001.15},
 acmid = {1128563},
 publisher = {IEEE Computer Society},
 address = {Washington, DC, USA},
} 

@article{PIE,
 author = {Van Craeynest, Kenzo and Jaleel, Aamer and Eeckhout, Lieven and Narvaez, Paolo and Emer, Joel},
 title = {Scheduling heterogeneous multi-cores through Performance Impact Estimation (PIE)},
 journal = {SIGARCH Comput. Archit. News},
 issue_date = {June 2012},
 volume = {40},
 number = {3},
 month = jun,
 year = {2012},
 issn = {0163-5964},
 pages = {213--224},
 numpages = {12},
 url = {http://doi.acm.org/10.1145/2366231.2337184},
 doi = {10.1145/2366231.2337184},
 acmid = {2337184},
 publisher = {ACM},
 address = {New York, NY, USA},
} 

@inproceedings{EXOCHI,
 author = {Wang, Perry H. and Collins, Jamison D. and Chinya, Gautham N. and Jiang, Hong and Tian, Xinmin and Girkar, Milind and Yang, Nick Y. and Lueh, Guei-Yuan and Wang, Hong},
 title = {EXOCHI: architecture and programming environment for a heterogeneous multi-core multithreaded system},
 booktitle = {Proceedings of the 2007 ACM SIGPLAN conference on Programming language design and implementation},
 series = {PLDI '07},
 year = {2007},
 isbn = {978-1-59593-633-2},
 location = {San Diego, California, USA},
 pages = {156--166},
 numpages = {11},
 url = {http://doi.acm.org/10.1145/1250734.1250753},
 doi = {10.1145/1250734.1250753},
 acmid = {1250753},
 publisher = {ACM},
 address = {New York, NY, USA},
 keywords = {GPU, heterogeneous multi-cores, openMP},
} 

@article{scalableCUDA,
 author = {Nickolls, John and Buck, Ian and Garland, Michael and Skadron, Kevin},
 title = {Scalable Parallel Programming with CUDA},
 journal = {Queue},
 issue_date = {March/April 2008},
 volume = {6},
 number = {2},
 month = mar,
 year = {2008},
 issn = {1542-7730},
 pages = {40--53},
 numpages = {14},
 url = {http://doi.acm.org/10.1145/1365490.1365500},
 doi = {10.1145/1365490.1365500},
 acmid = {1365500},
 publisher = {ACM},
 address = {New York, NY, USA},
} 

@inproceedings{brook,
 author = {Buck, Ian and Foley, Tim and Horn, Daniel and Sugerman, Jeremy and Fatahalian, Kayvon and Houston, Mike and Hanrahan, Pat},
 title = {Brook for GPUs: stream computing on graphics hardware},
 booktitle = {ACM SIGGRAPH 2004 Papers},
 series = {SIGGRAPH '04},
 year = {2004},
 location = {Los Angeles, California},
 pages = {777--786},
 numpages = {10},
 url = {http://doi.acm.org/10.1145/1186562.1015800},
 doi = {10.1145/1186562.1015800},
 acmid = {1015800},
 publisher = {ACM},
 address = {New York, NY, USA},
 keywords = {Data Parallel Computing, GPU Computing, Brook, Programmable Graphics Hardware, Stream Computing},
} 

@INPROCEEDINGS{sampson-HPCA-ECOCORES, 
author={Sampson, J. and Venkatesh, G. and Goulding-Hotta, N. and Garcia, S. and Swanson, S. and Taylor, M.B.}, 
booktitle={High Performance Computer Architecture (HPCA), 2011 IEEE 17th International Symposium on}, 
title={Efficient complex operators for irregular codes}, 
year={2011}, 
pages={491-502}, 
keywords={cache storage;coprocessors;pipeline processing;L0 cache;c-cores;cachelets;complex fat operators;conservation cores;coprocessors;critical path length;irregular codes;load-use delay;selective depipelining technique;Clocks;Hardware;Memory management;Pipeline processing;Registers;Silicon}, 
doi={10.1109/HPCA.2011.5749754}, 
ISSN={1530-0897},}

@inproceedings{Vasilieospeakpowermicro2010,
 author = {Kontorinis, Vasileios and Shayan, Amirali and Tullsen, Dean M. and Kumar, Rakesh},
 title = {Reducing peak power with a table-driven adaptive processor core},
 booktitle = {Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture},
 series = {MICRO 42},
 year = {2009},
 isbn = {978-1-60558-798-1},
 location = {New York, New York},
 pages = {189--200},
 numpages = {12},
 url = {http://doi.acm.org/10.1145/1669112.1669137},
 doi = {10.1145/1669112.1669137},
 acmid = {1669137},
 publisher = {ACM},
 address = {New York, NY, USA},
 keywords = {adaptive architectures, decoupling capacitance, peak power, resource resizing, voltage variation},
} 

@article{10x10,
  title={The 10x10 Foundation for Heterogeneity: Clustering Applications by Computation and Memory Behavior},
  author={Guha, Apala and Cicotti, Pietro and Snavely, Allan and Chien, Andrew A},
  journal={University of Chicago, Tech. Rep. TR-2012-01},
  year={2012}
}

@article{variable2011multi,
  title={A multi-core CPU architecture for low power and high performance},
  author={Variable, SMP},
  journal={Whitepaper-http://www. nvidia. com},
  year={2011}
}


---------------------------------------------------------------
---- CoE Grant additions start here ---------------------------
---------------------------------------------------------------


@INPROCEEDINGS{Razor, 
author={Ernst, D. and Nam Sung Kim and Das, S. and Pant, S. and Rao, R. and Pham, T. and Ziesler, C. and Blaauw, D. and Austin, T. and Flautner, K. and Mudge, T.}, 
booktitle={Microarchitecture, 2003. MICRO-36. Proceedings. 36th Annual IEEE/ACM International Symposium on}, 
title={{Razor: a low-power pipeline based on circuit-level timing speculation}}, 
year={2003}, 
month={Dec}, 
pages={7-18}, 
keywords={comparators (circuits);flip-flops;logic design;low-power electronics;pipeline processing;system-on-chip;timing circuits;0.18 microns;Razor;SPICE-level Kogge-Stone adder model;circuit delay;circuit timing errors;circuit-level timing speculation;clock frequencies;critical voltage;data dependence;double-samples pipeline stage;dymanic correction;dynamic detection;dynamic voltage scaling;embedded processors;environmental variations;error rate monitoring;error recovery;full-custom multiplier;low-power pipeline;maximum power savings;metastability-tolerant comparator;pipeline mispeculation recovery mechanism;power aware computing;process variations;program state;silicon integration;supply voltage;systems-on-chip design;time-borrowing delayed clock;voltage margins;Clocks;Delay;Dynamic voltage scaling;Error correction;Frequency;Pipelines;Silicon;Timing;Tuned circuits;Voltage control}, 
doi={10.1109/MICRO.2003.1253179},}

@ARTICLE{RazorII, 
author={Das, S. and Tokunaga, C. and Pant, S. and Wei-Hsiang Ma and Kalaiselvan, S. and Lai, K. and Bull, D.M. and Blaauw, D.T.}, 
journal={Solid-State Circuits, IEEE Journal of}, 
title={{RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance}}, 
year={2009}, 
month={Jan}, 
volume={44}, 
number={1}, 
pages={32-48}, 
keywords={error correction;error detection;flip-flops;Razor II flip-flop;adaptive method;architectural correction;energy saving;in situ error detection;register SER;state-holding latch node;supply voltage control;variation-induced delay error;Circuits;Delay;Dynamic voltage scaling;Error correction;Flip-flops;Fluctuations;Frequency;Safety;Temperature;Voltage control;Adaptive circuits;dynamic voltage and frequency scaling (DVFS);process variations;self-tuning processor;single event upsets}, 
doi={10.1109/JSSC.2008.2007145}, 
ISSN={0018-9200},}

@inproceedings{ReCycle_ISCA07,
 author = {Tiwari, Abhishek and Sarangi, Smruti R. and Torrellas, Josep},
 title = {ReCycle:: Pipeline Adaptation to Tolerate Process Variation},
 booktitle = {Proceedings of the 34th Annual International Symposium on Computer Architecture},
 series = {ISCA '07},
 year = {2007},
 isbn = {978-1-59593-706-3},
 location = {San Diego, California, USA},
 pages = {323--334},
 numpages = {12},
 url = {http://doi.acm.org/10.1145/1250662.1250703},
 doi = {10.1145/1250662.1250703},
 acmid = {1250703},
 publisher = {ACM},
 address = {New York, NY, USA},
 keywords = {clock skew, pipeline, process variation},
} 

@inproceedings{CircuitTechniques_DAC09,
 author = {Bowman, Keith and Tschanz, James and Wilkerson, Chris and Lu, Shih-Lien and Karnik, Tanay and De, Vivek and Borkar, Shekhar},
 title = {Circuit Techniques for Dynamic Variation Tolerance},
 booktitle = {Proceedings of the 46th Annual Design Automation Conference},
 series = {DAC '09},
 year = {2009},
 isbn = {978-1-60558-497-3},
 location = {San Francisco, California},
 pages = {4--7},
 numpages = {4},
 url = {http://doi.acm.org/10.1145/1629911.1629915},
 doi = {10.1145/1629911.1629915},
 acmid = {1629915},
 publisher = {ACM},
 address = {New York, NY, USA},
 keywords = {dynamic variations, error correction, error detection, error recovery, error-detection sequential, parameter variations, replica paths, resilient circuits, timing errors, variation sensors, variation-tolerant circuits},
} 

@inproceedings{Relax_ISCA2010,
 author = {de Kruijf, Marc and Nomura, Shuou and Sankaralingam, Karthikeyan},
 title = {Relax: An Architectural Framework for Software Recovery of Hardware Faults},
 booktitle = {Proceedings of the 37th Annual International Symposium on Computer Architecture},
 series = {ISCA '10},
 year = {2010},
 isbn = {978-1-4503-0053-7},
 location = {Saint-Malo, France},
 pages = {497--508},
 numpages = {12},
 url = {http://doi.acm.org/10.1145/1815961.1816026},
 doi = {10.1145/1815961.1816026},
 acmid = {1816026},
 publisher = {ACM},
 address = {New York, NY, USA},
 keywords = {reliability, software recovery},
} 

@INPROCEEDINGS{ABK_SlackRedistribution_ASPDAC2010, 
author={Kahng, A.B. and Seokhyeong Kang and Kumar, R. and Sartori, J.}, 
booktitle={Design Automation Conference (ASP-DAC), 2010 15th Asia and South Pacific}, 
title={{Slack redistribution for graceful degradation under voltage overscaling}}, 
year={2010}, 
month={Jan}, 
pages={825-831}, 
keywords={fault tolerance;integrated circuit design;integrated circuit reliability;critical voltage;error-tolerance mechanism;graceful degradation;maximum error rate;modern digital IC designs;near-critical timing path;power-aware slack redistribution;system reliability;timing error rate;voltage overscaling;voltage scaling;Degradation;Digital integrated circuits;Energy consumption;Error analysis;Error correction;Microprocessors;Power system reliability;Routing;Timing;Voltage}, 
doi={10.1109/ASPDAC.2010.5419690},}

@INPROCEEDINGS{ABK_GroundUpDesignHPCA2010,
author={Kahng, A.B. and Seokhyeong Kang and Kumar, R. and Sartori, J.}, 
booktitle={High Performance Computer Architecture (HPCA), 2010 IEEE 16th International Symposium on}, 
title={{Designing a processor from the ground up to allow voltage/reliability tradeoffs}}, 
year={2010}, 
month={Jan}, 
pages={1-11}, 
keywords={energy conservation;error analysis;microprocessor chips;optimisation;error rate;error-tolerance mechanism;operational errors;optimization;power consumption;power savings;power-aware slack redistribution;processor design;reliability tradeoff;soft architectures;timing errors;voltage scaling;voltage tradeoff;Circuits;Error analysis;Error correction;Flip-flops;Frequency;Latches;Process design;Timing;Virtual colonoscopy;Voltage}, 
doi={10.1109/HPCA.2010.5416652}, 
ISSN={1530-0897},}

@INPROCEEDINGS{Torellas_EVAL_MICRO08, 
author={Sarangi, S. and Greskamp, B. and Tiwari, A. and Torrellas, J.}, 
booktitle={Microarchitecture, 2008. MICRO-41. 2008 41st IEEE/ACM International Symposium on}, 
title={{EVAL: Utilizing processors with variation-induced timing errors}}, 
year={2008}, 
month={Nov}, 
pages={423-434}, 
keywords={computer architecture;learning (artificial intelligence);microprocessor chips;performance evaluation;timing;EVAL;high-dimensional dynamic adaptation;integrated circuits;machine learning;microarchitecture techniques;parameter variation;performance maximization;power frequency;power minimization;processor frequency;processor performance;processors;transistor budget;variation-induced timing errors;worst-case parameter values;Computer errors;Computer science;Costs;Frequency;Logic;Microarchitecture;Process design;Temperature;Timing;Voltage}, 
doi={10.1109/MICRO.2008.4771810}, 
ISSN={1072-4451},}

@inproceedings{ABK_RecoveryDrivenDesign_DAC2010,
 author = {Kahng, Andrew B. and Kang, Seokhyeong and Kumar, Rakesh and Sartori, John},
 title = {Recovery-driven Design: A Power Minimization Methodology for Error-tolerant Processor Modules},
 booktitle = {Proceedings of the 47th Design Automation Conference},
 series = {DAC '10},
 year = {2010},
 isbn = {978-1-4503-0002-5},
 location = {Anaheim, California},
 pages = {825--830},
 numpages = {6},
 url = {http://doi.acm.org/10.1145/1837274.1837481},
 doi = {10.1145/1837274.1837481},
 acmid = {1837481},
 publisher = {ACM},
 address = {New York, NY, USA},
 keywords = {power minimization, recovery-driven design},
} 

@inproceedings{Brooks_Tribeca_MICRO09,
 author = {Gupta, Meeta S. and Rivers, Jude A. and Bose, Pradip and Wei, Gu-Yeon and Brooks, David},
 title = {Tribeca: Design for PVT Variations with Local Recovery and Fine-grained Adaptation},
 booktitle = {Proceedings of the 42Nd Annual IEEE/ACM International Symposium on Microarchitecture},
 series = {MICRO 42},
 year = {2009},
 isbn = {978-1-60558-798-1},
 location = {New York, New York},
 pages = {435--446},
 numpages = {12},
 url = {http://doi.acm.org/10.1145/1669112.1669168},
 doi = {10.1145/1669112.1669168},
 acmid = {1669168},
 publisher = {ACM},
 address = {New York, NY, USA},
} 



@inproceedings{Swaminathan_SystemLevelTFET_ISCA14,
 author = {Swaminathan, Karthik and Liu, Huichu and Sampson, Jack and Narayanan, Vijaykrishnan},
 title={{An Examination of the Architecture and System-level Tradeoffs of Employing Steep Slope Devices in 3D CMPs}},
 booktitle = {Proceedings of the 41st Annual International Symposium on Computer Architecture},
 series = {ISCA '14},
 year = {2014},
 location = {Minneapolis, Minnesota},
 publisher = {ACM},
 address = {New York, NY, USA},
}

@INPROCEEDINGS{Swaminathan_ModelingTFET_DATE14, 
author={Swaminathan, Karthik and Kim, Moon Seok and Chandramoorthy, Nandhini and Sedighi, Behnam and Perricone, Robert and Sampson, Jack and Narayanan, Vijaykrishnan}, 
booktitle={Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014}, 
title={{Modeling Steep Slope Devices: From Circuits to Architectures}}, 
year={2014}, 
month={March}, 
pages={1-6}, 
keywords={CMOS integrated circuits;Libraries;Microprocessors;Multicore processing;Performance evaluation;Program processors}, 
doi={10.7873/DATE2014.149},}


@INPROCEEDINGS{Swaminathan_SteepSlope_DAC14, 
author={Swaminathan, Karthik and Liu, Huichu and Li, Xueqing and Kim, Moon Seok and Sampson, Jack and Narayanan, Vijaykrishnan}, 
booktitle={To appear in The Design Automation Conference (DAC)}, 
title={{Steep Slope Devices: Enabling New Architectural Paradigms}}, 
year={2014}, 
month={June}, 
}

@inproceedings{Zeitzoff-IJHSES2002-MOSFET_Scaling, 
 author = {P. M. Zeitzoff and J. A. Hutchby and H. R. Huff}, 
 title = "{MOSFET and Front-end Process Integration: Scaling trends, challenges, and potential solutions through the end of the roadmap}", 
 booktitle = "{International Journal of High Speed Electronics and Systems}", 
 year = {2002},
 month={June},
 }

@INPROCEEDINGS{Borkar-DAC2003-Variations, 
 author={Borkar, S. and Karnik, T. and Narendra, S. and Tschanz, J. and Keshavarzi, A. and De, V.}, 
 booktitle={Design Automation Conference, 2003. Proceedings}, 
 title={{Parameter variations and impact on circuits and microarchitecture}}, 
 year={2003}, 
 month={June}, 
 pages={338-342}, 
}

 
@ARTICLE{Hisamoto-TED2000-FinFETs, 
author={Hisamoto, D. and Wen-Chin Lee and Kedzierski, J. and Takeuchi, H. and Asano, K. and Kuo, C. and Anderson, Erik and Tsu-Jae King and Bokor, J. and Chenming Hu}, 
journal={Electron Devices, IEEE Transactions on}, 
title={{FinFET-a self-aligned double-gate MOSFET scalable to 20 nm}}, 
year={2000}, 
month={Dec}, 
volume={47}, 
number={12}, 
pages={2320-2325}, 
}


@ARTICLE{Vega-TED2009-DSDT, 
author={Vega, R.A. and Liu, K. and Tsu-Jae King Liu}, 
journal={Electron Devices, IEEE Transactions on}, 
title={{Dopant-Segregated Schottky Source/Drain Double-Gate MOSFET Design in the Direct Source-to-Drain Tunneling Regime}}, 
year={2009}, 
month={Sept}, 
volume={56}, 
number={9}, 
pages={2016-2026}, 
}

@ARTICLE{Dreslinski-PIEEE2010-NTC, 
author={Dreslinski, R.G. and Wieckowski, M. and Blaauw, D. and Sylvester, D and Mudge, T.}, 
journal={Proceedings of the IEEE}, 
title={{Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits}}, 
year={2010}, 
month={Feb}, 
volume={98}, 
number={2}, 
pages={253-266}, 
}

@INPROCEEDINGS{Mookerjea-DRC2008-TFETs, 
author={Mookerjea, S. and Datta, S.}, 
booktitle={Device Research Conference, 2008}, 
title={{Comparative Study of Si, Ge and InAs based Steep SubThreshold Slope Tunnel Transistors for 0.25V Supply Voltage Logic Applications}}, 
year={2008}, 
month={June}, 
pages={47-48}, 
}

@inproceedings{Singh-ASPDAC2010-TFETSRAM,
 author = {Singh, J. and Ramakrishnan, K. and Mookerjea, S. and Datta, S. and Vijaykrishnan, N. and Pradhan, D.},
 title = {{A Novel Si-tunnel FET Based SRAM Design for Ultra Low-power 0.3V VDD Applications}},
 booktitle = {Proceedings of the 2010 Asia and South Pacific Design Automation Conference},
 series = {ASPDAC '10},
 year = {2010},
 location = {Taipei, Taiwan},
 pages = {181--186},
 publisher = {IEEE Press},
 address = {Piscataway, NJ, USA},
} 


@ARTICLE{Mookerjea-EDL2009-TFETMillerCap, 
author={Mookerjea, S. and Krishnan, R. and Datta, S. and Narayanan, V.}, 
journal={Electron Device Letters, IEEE}, 
title={{On Enhanced Miller Capacitance Effect in Interband Tunnel Transistors}}, 
year={2009}, 
month={Oct}, 
volume={30}, 
number={10}, 
pages={1102-1104}, 
}

@ARTICLE{Khatami-TED2009-TFETCircuits, 
author={Khatami, Y. and Banerjee, K.}, 
journal={Electron Devices, IEEE Transactions on}, 
title={{Steep Subthreshold Slope n- and p-Type Tunnel-FET Devices for Low-Power and Energy-Efficient Digital Circuits}}, 
year={2009}, 
month={Nov}, 
volume={56}, 
number={11}, 
pages={2752-2761}, 
}


@book{RabaeyBook,
  added-at = {2010-03-21T11:37:19.000+0100},
  author = {Rabaey, Jan M. and Chandrakasan, Anantha and Nikolic, Borivoje},
  biburl = {http://www.bibsonomy.org/bibtex/2a4b6d94ef6a1028b9dd0fd8d19e63fb1/heartsoar},
  edition = {2ed},
  interhash = {783ae3be223d82d91a21986acbbaf13a},
  intrahash = {a4b6d94ef6a1028b9dd0fd8d19e63fb1},
  keywords = {},
  publisher = {Prentice Hall},
  title = {Digital integrated circuits- A design perspective},
  year = 2004
}

@article{Datta-MicroRel2014-TFET,
title = "Tunnel {FET} technology: A Reliability Perspective ",
journal = "Microelectronics Reliability ",
volume = "54",
number = "5",
pages = "861 - 874",
year = "2014",
note = "",
author = "Suman Datta and Huichu Liu and Vijaykrishnan Narayanan"
}


